1. Field of the Invention
The present invention relates to a semiconductor memory device provided with a memory cell including a variable resistance element having two terminals, that can store information by varying its electric resistan ce between a first state and a second state when voltage having different polarities are separately applied to both ends thereof, and a select transistor whose source or drain is connected to one end of the variable resistance element.
2. Description of the Related Art
Nonvolatile semiconductor memory devices including typically flash memories have widely been marketed for use in computers, communications apparatuses, measuring apparatuses, automatic controlling apparatuses, and house-hold appliances designed for personal use, as they are large in the storage capacity and small in the overall size. There is an increasing demand for providing less expensive, larger storage size nonvolatile semiconductor memory devices. This is because such nonvolatile semiconductor memory devices are electrically writable and capable of holding data when they have been de-energized and can thus be functioned as nonvolatile data storages or program storages where initial settings for operating the apparatuses are stored in portable apparatuses such as memory cards or mobile telephones.
Also, as some other types of the nonvolatile semiconductor memories have been proposed employing novel materials, one of them is promisingly known an RRAM (resistance random access memory). The RRAM is based on a variable resistance element for changing the resistance to develop a memory function when receiving a current greater than the read current and favorable for future use as improved in the operation speed, the storage size, the power consumption, and the performance potential.
Disclosed in Japanese Patent Laid-open Publication No. 2004-185755 (referred to as a prior art citation hereinafter) is a type of RRAM which comprises one or more arrays of nonvolatile memory cells, each cell including a variable resistance element, arranged in rows and columns and accompanied with a number of word lines and a number of bit lines arranged along the rows and the columns respectively for selecting one or more of the memory cells.
For instance, the variable resistance element of each memory cell in the RRAM is connected at one end to the source (or the drain) of a select transistor for storage of information through varying the electrical resistance. Also in the memory cell array, either the other end of the variable resistance element or the drain (or the source) of the select transistor is connected to a common bit line extending along one column while the other is connected to a common source line. The gate of the select transistor is connected to a common word line extending along one row. When the word line, the bit line, and the source line connected to its memory cell array of interest in the above arrangement are applied with their respective levels of the voltage determined to match the requirements of voltage application, the stored data in the memory cell can be written or read out.
For example, the memory cells in the memory cell array of the prior art citation are shown in FIG. 23. More particularly, as shown in FIG. 23, the variable resistance element 11 is connected at one end to the source of the select transistor 12 to build up a memory cell 10. The variable resistance elements 11 are connected at the other end to source lines SL1, SL2 while the select transistors 12 are connected at the drain to bit lines BL1 to BL4. Since the memory cell in the prior art citation is composed mainly of a series circuit of the variable resistance element and the select transistor, its select transistors aligned along an unselected row remain turned off (not conducted) thus to disconnect the current path which extends through the variable resistance elements in the memory cells other than the selected memory cell. This prevents the unselected memory cells connected to the same bit lines from interrupting the read action of the selected memory cell. Moreover, since the select transistor is connected between the bit lines and the variable resistance element in each memory cell, the variable resistance elements in the unselected memory cells are electrically isolated from the bit lines along the selected column to which the readout voltage is applied. This permits the variable resistance elements to remain free from any stress of the voltage, thus increasing the reliability in the data storage performance.
The RRAM in the prior art citation is proposed in which the variable resistance element is varied in the electric resistance by the action of electrical stress and its resistance level remains held after the removal of the electrical stress. The variable resistance element is made of, for example, an oxide material of a perovskite structure containing manganese which may be selected from Pr(1·x)CaxMnO3, La(1·x)CaxMnO3, La(1·x·y)CaxPbyMnO3 (where x<1, y<1, and x+y<1), Sr2FeMoO6,and Sr2FeWO6, or more specifically Pr0.7Ca0.3MnO3, La0.65Ca0.35MnO3, and La0.65Ca0.175Pb0.175MnO3 in manganese oxide layer form.
The reading action on the memory cell array shown in FIG. 23 will now be described. The action starts with making the bit line select transistor 4 conductive which is connected to the selected bit line in order to supply the selected bit line connected to the memory cell to be read with a bias voltage. Simultaneously, the selected word line connected to the gate of the select transistor 3 in the memory cell to be read is turned to the high level by a word line driver 5 in order to make the select transistor 3 conductive. In addition, the source line is supplied with a reference voltage or 0 V (of the grounding voltage). As the result, a current path for the reading action is established extending from the selected bit line at the bias voltage through the select transistor 3 and the variable resistance element 2 in the memory cell to be read to the source line at the grounding voltage level. Meanwhile, as for the unselected memory cells, the unselected word lines are turned to the low level, for example, 0 V by the word line driver 5 and the unselected bit lines are turned to the low level, for example, 0 V or the open state (at a high impedance level). As a result, there is no current path from the selected bit line to the source line other than the current path for the reading action to pass through the variable resistance element in the memory cell to be read. As the change in the electric resistance in the variable resistance element in the memory cell to be read is interpreted to a change in the current which runs through the bit line in response to the application of voltages across the bit line, the word line, an the source line, the current change is analyzed by the readout circuit thus to correctly pick the information from the memory cell to be read. Moreover, since the variable resistance elements in the unselected memory cells and the selected bit line are electrically disconnected, the variable resistance elements in the unselected memory cells directly receive no voltage stress from the bit line even if the reading action is repeatedly carried out with the same bit line. Accordingly, any change in the resistance of the variable resistance element or the erase or the loss of information stored in the variable resistance element caused by the voltage stress will significantly be minimized. In other words, the semiconductor memory device will be improved in the reliability of data storage.
However, the semiconductor memory device described above is contemplated for inhibiting the loss of information stored in the memory cells not to be read during the reading action on the selected memory cell to be read but fails to avoid the loss of information stored in the selected memory cell to be read. Accordingly, when the selected memory cell to be read is repeatedly subjected to the reading action a number of times, its stored information may be lost due to a change in the resistance caused by the readout voltage which is applied directly to the variable resistance element, whereby its reliability of data storage will be declined.
The prior art citation protects the variable resistance element in the memory cell not to be read from directly receiving a stress of voltage from the bit line and can thus inhibit any change in the resistance or the loss of information stored in the variable resistance element. It can however fail to eliminate the probability of the loss of information stored in the variable resistance element in the selected memory cell to be read.
The loss of information stored in the selected memory cell may be triggered by the fact that, while the writing action on the variable resistance element is carried out through varying the resistance level of the variable resistance element or more particularly applying a first readout voltage to between the two ports of the variable resistance element for shifting the resistance level from a first state to a second state and applying a second readout voltage for shifting the resistance level from the second state to the first state, the action of reading the resistance level of the variable resistance element is equally carried out through applying the readout voltage to between the two ports of the variable resistance element. In brief, the loss may be caused by the voltage application to the variable resistance element which is carried out in the writing action and the reading action element in the same way although the absolute values of the applied voltages are different between the actions. Accordingly, when the reading action is repeatedly conducted, the resistance level or the information stored in the variable resistance element may be lost at higher possibility.